74ABT2952 Datasheet | NXP Semiconductors

FEATURES - 8-bit registered transceiver - Independent registers for A and B buses - Output capability: +64m A/- 32m A - Latch-up protection exceeds 500m A per JEDEC Std 17 - ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The 74ABT2952 high-performance Bi CMOS device bines low static and dynamic power dissipation with high speed and high output drive. The 74ABT2952 device is an 8-bit registered transceiver. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (CEXX) is Low. The data is then present at the 3-State output buffers, but is only accessible when the Output Enable (OEXX) is Low. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. - Power-up 3-State - Power-up reset - Live insertion/extraction permitted QUICK REFERENCE DATA SYMBOL t PLH t PHL CIN CI/O ICCZ PARAMETER Propagation delay CPBA to An or CPAB to Bn Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50p F; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL UNIT 5.7 4 7 110 ns p F p F µA ORDERING INFORMATION PACKAGES 24-Pin Plastic DIP 24-Pin plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C OUTSIDE NORTH AMERICA 74ABT2952 N 74ABT2952 D 74ABT2952 DB 74ABT2952 PW NORTH AMERICA 74ABT2952 N 74ABT2952 D 74ABT2952 DB 7ABT2952PW DH DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1 PIN CONFIGURATION B7 B6 B5 B4 B3 B2 B1 B0 OEAB 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 VCC A7 A6 A5 A4 A3 A2 A1 A0 OEBA CPBA CEBA PIN DESCRIPTION PIN NUMBER 10, 14 11, 13 16, 17, 18, 19, 20, 21, 22, 23 1, 2, 3, 4, 5, 6, 7, 8 9, 15 12 24 SYMBOL CPAB / CPBA CEAB / CEBA A0 - A7 NAME AND FUNCTION Clock...