Philips Semiconductors
Octal transparent latch (3-State)
Product specification
74ABT373A
FEATURES
• 8-bit transparent latch
• 3-State output buffers
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up reset
• Live insertion/extraction permitted
DESCRIPTION
The 74ABT373A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT373A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE)
control gates.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
QUICK REFERENCE DATA
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
SYMBOL
tPLH
tPHL
CIN
COUT
ICCZ
PARAMETER
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.2
3.6
4
7
100
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT373A N
–40°C to +85°C
74ABT373A D
–40°C to +85°C
74ABT373A DB
–40°C to +85°C
74ABT373A PW
NORTH AMERICA
74ABT373A N
74ABT373A D
74ABTD373A B
7ABT373APW DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 E
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1
3, 4, 7, 8, 13,
14, 17, 18
OE
D0-D7
Output enable input (active-Low)
Data inputs
2, 5, 6, 9, 12,
15, 16, 19
11
10
Q0-Q7
E
GND
Data outputs
Enable input (active-High)
Ground (0V)
20 VCC Positive supply voltage
SA00059
1995 Feb 17
2 853-1454 14852
