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NXP Semiconductors Electronic Components Datasheet

74ABT834 Datasheet

Octal inverting transceiver

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Philips Semiconductors Advanced BiCMOS Products
Octal inverting transceiver with parity
generator/checker (3–State)
Objective specification
74ABT834
FEATURES
Low static and dynamic power dissipation
with high speed and high output drive
Open–collector ERROR output
Output capability: +64mA/–32mA
Latch–up protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883C Method 3015.6 and 200 V per
Machine Model
Power up/down 3–State
DESCRIPTION
The 74ABT834 high–performance BiCMOS
device combines low static and dynamic
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
Output capacitance
Total supply current
power dissipation with high speed and high
output drive.
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for bus–oriented applications.
When Output Enable A (OEA) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity
output (PARITY) when OEB is Low. When
OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
sent to the input of a storage register. If a
Low–to–High transition happens at the clock
input (CP), the error data is stored in the
register and the Open–collector error flag
(ERROR) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
If both OEA and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
CL = 50pF; VCC = 5V
VI = 0V or VCC
VI = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.4
7.4
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24–pin plastic DIP (300mil)
24–pin plastic SOL (300mil)
PIN CONFIGURATION
CONDITIONS
Tamb = 25°C; GND = 0V
–40°C to +85°C
–40°C to +85°C
LOGIC SYMBOL
ORDER CODE
74ABT834N
74ABT834D
OEA 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
ERROR 10
CLEAR 11
GND 12
24 VCC
23 B0
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 PARITY
14 OEB
13 CP
TOP VIEW
June 9, 1992
23456789
A0 A1 A2 A3 A4 A5 A6 A7
14 OEB
1 OEA
PARITY
15
11 CLEAR
ERROR
10
13 CP
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
1


NXP Semiconductors Electronic Components Datasheet

74ABT834 Datasheet

Octal inverting transceiver

No Preview Available !

Philips Semiconductors Advanced BiCMOS Products
Octal inverting transceiver with parity
generator/checker (3–State)
Objective specification
74ABT834
PIN DESCRIPTION
SYMBOL
PIN NUMBER
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
OEA
1
OEB
14
PARITY
15
ERROR
10
CLEAR
11
CP 13
GND
12
VCC
24
NAME AND FUNCTION
A port 3–State inputs/outputs
B port 3–State inputs/outputs
Enables the A outputs when Low
Enables the B outputs when Low
Parity output
Error output
Clears the error flag register when Low
Clock input
Ground (0V)
Positive supply voltage
FUNCTION TABLE
MODE
A data to B bus and generate odd parity
output
B data to A bus and check for parity error1
A bus and B bus disabled2
A data to B bus and generate inverted
parity output
OEB
L
H
H
L
OEA
H
L
H
L
INPUTS
An
Σ of Highs
Odd
Even
NA
(output)
X
Odd
Even
Bn + Parity
Σ of Lows
NA
(output)
Odd
Even
X
NA
(output)
An
NA
(input)
Bn
Z
NA
(input)
OUTPUTS
Bn
An
NA
(input)
Z
An
PARITY
H
L
NA
(input)
Z
L
H
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
MODE
CLEAR
CP
Bn + Parity
Σ of Lows
Point ”P”
Pre–state
ERRORn–1
Sample
H
H
HX
Odd
Even
X
HH
LX
XL
Hold
H
X
XX
Clear
LX
X
XX
ERROR
OUTPUT
H
L
L
NC
H
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
NA = Not applicable
NC = No change
Z = High impedance ”off” state
= Low–to–High clock transition
= Not a Low–to–High clock transition
June 9, 1992
2


Part Number 74ABT834
Description Octal inverting transceiver
Maker NXP
Total Page 7 Pages
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