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NXP Semiconductors Electronic Components Datasheet

74ABT841 Datasheet

10-bit bus interface latch

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Philips Semiconductors
10-bit bus interface latch (3-State)
Product specification
74ABT841
FEATURES
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Slim DIP 300 mil package
Broadside pinout
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled;
VO = 0V or VCC
Outputs disabled; VCC = 5.5V
TYPICAL
4.1
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT841 N
–40°C to +85°C
74ABT841 D
–40°C to +85°C
74ABT841 DB
–40°C to +85°C
74ABT841 PW
NORTH AMERICA
74ABT841 N
74ABT841 D
74ABT841 DB
74ABT841PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
TOP VIEW
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
13
OE
D0-D9
Output enable input
(active-Low)
Data inputs
Q0-Q9
LE
Data outputs
Latch enable input (active
falling edge)
12 GND Ground (0V)
24 VCC Positive supply voltage
SA00247
1995 Sep 06
1 853-1628 15703


NXP Semiconductors Electronic Components Datasheet

74ABT841 Datasheet

10-bit bus interface latch

No Preview Available !

Philips Semiconductors
10-bit bus interface latch (3-State)
Product specification
74ABT841
LOGIC SYMBOL
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13 LE
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
LOGIC SYMBOL (IEEE/IEC)
SA00244
FUNCTION TABLE
INPUTS
OE LE
Dn
OUTPUTS
Q0 – Q9
OPERATING
MODE
LH
L
LH H
L
H
Transparent
L
L
l
h
L
H
Latched
HX
X
Z High impedance
LL
X
NC Hold
H=
h=
L=
l=
=
NC=
X=
Z=
High voltage level
High voltage level one set-up time prior to the High-to-Low LE
transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low LE
transition
High-to-Low LE transition
No change
Don’t care
High impedance “off” state
1
EN
13
C1
2 1D
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
SA00245
1995 Sep 06
2


Part Number 74ABT841
Description 10-bit bus interface latch
Maker NXP
Total Page 6 Pages
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