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74ABTH16899 - 18-bit latched transceiver

Download the 74ABTH16899 datasheet PDF. This datasheet also covers the 74ABTH variant, as both devices belong to the same 18-bit latched transceiver family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74ABT/H16899 has three principal modes of operation which are outlined below.

All modes apply to both the A-to-B and B-to-A directions.

Key Features

  • Symmetrical (A and B bus functions are identical).
  • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
  • Independent transparent latches.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ABTH-16899.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
INTEGRATED CIRCUITS www.DataSheet4U.net 74ABT16899 74ABTH16899 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification Supersedes data of 1997 Mar 28 IC23 Data Handbook 1998 Feb 25 Philips Semiconductors Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 FEATURES • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State.