74AHC08 Datasheet | NXP Semiconductors

FEATURES - ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V - Balanced propagation delays - All inputs have Schmitt-trigger actions - Inputs accepts voltages higher than VCC - For AHC only: operates with CMOS input levels - For AHCT only: operates with TTL input levels - Specified from - 40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT08 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 7A. The 74AHC/AHCT08 provide the 2-input AND function. FUNCTION TABLE See note 1. INPUT n A L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. n B L H L H OUTPUT n Y L L L H QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC08; 74AHCT08 TYPICAL SYMBOL t PHL/t PLH CI CO CPD PARAMETER propagation delay n A, n B to n Y input capacitance output capacitance power dissipation capacitance CL = 50 p F; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 p F; VCC = 5 V VI = VCC or GND 3.5 3.0 4.0 10 AHCT 5.0 3.0 4.0 12 ns p F p F p F UNIT Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in p F; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1, 4, 9 and 12 2, 5, 10 and 13 3, 6, 8 and 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC DESCRIPTION data inputs data inputs data outputs ground (0 V) DC supply voltage 1999 Sep 24 Philips Semiconductors Product specification Quad 2-input AND gate ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC08D 74AHC08PW 74AHCT08D 74AHCT08PW 74AHC08; 74AHCT08 PACKAGES NORTH AMERICA PINS 74AHC08D 74AHC08PW DH 74AHCT08D 74AHCT08PW DH 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1...