74AHC08 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET 74AHC08; 74AHCT08 Quad 2-input AND gate Product specification Supersedes data of 1998 Dec 18 File under Integrated Circuits, IC06 1999 Sep 24 Philips Semiconductors Product specification Quad 2-input AND gate Features - ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V - Balanced propagation delays - All inputs have Schmitt-trigger actions - Inputs accepts voltages higher than VCC - For AHC only: operates with CMOS input levels - For AHCT only: operates with TTL input levels - Specified from - 40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT08 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 7A. The 74AHC/AHCT08 provide the 2-input AND function. FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H OUTPUT nY L L L H QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC08; 74AHCT08 TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay nA, nB to nY input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V VI = VCC or GND 3.5 3.0 4.0 10 AHCT 5.0 3.0 4.0 12 ns pF pF pF UNIT Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1, 4, 9 and 12 2, 5, 10 and 13 3, 6, 8 and 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC...