Quad buffer/line driver; 3-state
• ESD protection:
exceeds 2000 V
exceeds 200 V
exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger
• Inputs accepts voltages higher than
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
The 74AHC/AHCT125 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT125 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE). A HIGH at n
causes the outputs to assume a
The ‘125’ is identical to the ‘126’ but
has active LOW enable inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
tPHL/tPLH propagation delay CL = 15 pF;
nA to nY
VCC = 5 V
3.0 3.0 ns
CI input capacitance VI = VCC or GND 3.0 3.0 pF
CO output capacitance
4.0 4.0 pF
CPD power dissipation CL = 50 pF; 10 12 pF
f = 1 MHz;
notes 1 and 2
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
See note 1.
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
1999 Sep 27