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74AHC126 Datasheet

Quad buffer/line driver; 3-state

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INTEGRATED CIRCUITS
DATA SHEET
74AHC126; 74AHCT126
Quad buffer/line driver; 3-state
Product specification
Supersedes data of 1999 Jan 12
File under Integrated Circuits, IC06
1999 Sep 29


NXP Semiconductors Electronic Components Datasheet

74AHC126 Datasheet

Quad buffer/line driver; 3-state

No Preview Available !

Philips Semiconductors
Quad buffer/line driver; 3-state
Product specification
74AHC126; 74AHCT126
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputs accepts voltages higher than
VCC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT126 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT126 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE) A LOW at nOE
causes the outputs to assume a
HIGH-impedance OFF state.
The ‘126’ is identical to the ‘125’ but
has active HIGH enable inputs.
FUNCTION TABLE
See note 1.
INPUTS
nOE
H
H
L
nA
L
H
X
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF state.
OUTPUT
nY
L
H
Z
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL PARAMETER
CONDITIONS
tPHL/tPLH
CI
CO
CPD
propagation delay CL = 15 pF;
nA to nY
VCC = 5 V
input capacitance VI = VCC or GND
output capacitance
power dissipation
capacitance
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
TYPICAL
UNIT
AHC AHCT
3.3 3.0 ns
3.0 3.0 pF
4.0 4.0 pF
10 12 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
PIN
1, 4, 10 and 13
2, 5, 9 and 12
3, 6, 8 and 11
7
14
SYMBOL
1OE to 4OE
1A to 4A
1Y to 4Y
GND
VCC
DESCRIPTION
output enable inputs (active HIGH)
data inputs
data outputs
ground (0 V)
DC supply voltage
1999 Sep 29
2


Part Number 74AHC126
Description Quad buffer/line driver; 3-state
Maker NXP
Total Page 16 Pages
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