74AHC245 Datasheet | NXP Semiconductors

FEATURES - ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V - Balanced propagation delays - All inputs have a Schmitt-trigger action - Inputs accepts voltages higher than VCC - For AHC only: operates with CMOS input levels - For AHCT only: operates with TTL input levels - Specified from - 40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT245 is a high-speed Si-gate CMOS device. The 74AHC/AHCT245 is an octal transceiver featuring non-inverting 3-state bus patible outputs in both send and receive directions. The 74AHC245/74AHCT245 features an Output Enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. FUNCTION TABLE See Note 1. INPUTS OE L L H DIR L H X 74AHC245; 74AHCT245 INPUTS/OUTPUTS An A=B inputs Z Bn inputs B=A Z QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL t PHL/t PLH CI CO CPD PARAMETER propagation delay An to Bn, Bn to An input capacitance output capacitance power dissipation capacitance CL = 50 p F; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 p F; VCC = 5 V 3.5 AHCT 5.0 3.5 4.0 15 ns p F p F p F UNIT VI = VCC or GND 3.5 4.0 12 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in p F; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 1999 Sep 28 Philips Semiconductors Product specification Octal bus transceiver; 3-state ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC245D 74AHC245PW 74AHCT245D 74AHCT245PW PINNING PIN 1 2 to 9 10 11 to 18 19 20 DIR A0 to A7 GND B7 to B0 OE VCC SYMBOL 74AHC245; 74AHCT245 PACKAGES NORTH AMERICA...