74ALS257 Datasheet | NXP Semiconductors

DESCRIPTION The 74ALS257 is a quad 2-input multiplexer which selects 4 bits of data from one of two sources under the control of a mon select input (S). The output enable input (OE) is active when Low. When OE is High, all of the outputs (Yn) are forced to a High impedance state (3-State) regardless of all other input conditions. Moving data from two registers to a mon output bus is a typical use of the 74ALS257. The state of the select input determines the particular register from which data es. The device is the logic implementation of 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the select input. The 74ALS258 is similar but has inverting outputs (Yn). TYPE 74ALS257 74ALS258 74ALS257/74ALS258 TYPICAL PROPAGATION DELAY 7.0ns 7.0ns TYPICAL SUPPLY CURRENT (TOTAL) 7m A 7m A ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS257N, 74ALS258 74ALS257D, 74ALS258D 74ALS257DB, 74ALS258DB DRAWING NUMBER SOT38-4 SOT109-1 SOT338-1 16-pin plastic DIP 16-pin plastic SO 16-pin plastic SSOP Type II INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Ina, Inb, Inc, Ind S OE Ya - Yd, Ya - Yd Data inputs Select input Enable input Data outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 20/240 LOAD VALUE HIGH/LOW 20µA/0.1m A 20µA/0.1m A 20µA/0.1m A 0.4m A/24m A NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1m A in the Low state. PIN CONFIGURATION - 74ALS257 S I0a I1a Ya I0b I1b Yb GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OE I0d I1d Yd I0c I1c Yc PIN CONFIGURATION - 74ALS258 S I0a I1a Ya I0b I1b Yb GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OE I0d I1d Yd I0c I1c Yc SF00673 SC00079 1991 Feb 08 853- 1130 01670 Philips Semiconductors Product specification Data selector/multiplexer 74ALS257/74ALS258 LOGIC SYMBOL - 74ALS257 LOGIC SYMBOL -...