74ALS377 Datasheet | NXP Semiconductors

FEATURES - Ideal for addressable register applications - Enable for address and data synchronization applications - Eight edge-triggered D-type flip-flops - Buffered mon clock - See 74ALS273 for master reset version - See 74ALS373 for transparent latch version - See 74ALS374 for 3-State version DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation. TYPICAL SUPPLY CURRENT (TOTAL) 15m A PIN CONFIGURATION E Q0 1 2 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP D0 3 D1 4 Q1 Q2 5 6 D2 7 D3 8 Q3 9 GND 10 SF00350 ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS377N 74ALS377D 74ALS377DB DRAWING NUMBER TYPE 74ALS377 TYPICAL f MAX 95MHz 20-pin plastic DIP 20-pin plastic SOL 20-pin plastic SSOP Type II SOT146-1 SOT163-1 SOT339-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 - D7 CP E Q0 - Q7 Data inputs Clock pulse input (active rising edge) Latch enable input Data outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/2.0 1.0/1.0 1.0/1.0 130/240 LOAD VALUE HIGH/LOW 20µA/0.2m A 20µA/0.1m A 20µA/0.1m A 2.6m A/24m A NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1m A in the Low state. LOGIC SYMBOL 3 4 7 8 13 14 17 18 IEC/IEEE SYMBOL 1 11 G1 1C2 D0 11 1 CP E D1 D2 D3 D4 D5 D6...