74F148 Datasheet | NXP Semiconductors

FEATURES - Code conversions - Multi-channel D/A converter - Decimal-to-BCD converter - Cascading for priority encoding of “N” bits - Input enable capability - Priority encoding-automatic selection of highest priority input line - Output enable-active Low when all inputs are High - Group signal output-active when any input is Low DESCRIPTION The 74F148 8-input priority encoder accepts data from eight active-Low inputs and provides a binary representation on the three active-Low outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line I7 having the highest priority. A High on the Enable Input (EI) will force all outputs to the inactive (High) state and allow new data to settle without producing erroneous information at the outputs. A Group Signal (GS) output and an Enable Output (EO) are provided with the three data outputs. The GS is active-Low when any input is Low: this indicates when any input is active. The EO is active-Low when all inputs are High. Using the Enable Output along with the Enable Input allows priority encoding of N input signals. Both EO and GS are active-High when the Enable Input is High. PIN CONFIGURATION I4 I5 I6 I7 EI A2 A1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC EO GS I3 I2 I1 I0 A0 SF00181 TYPE 74F148 TYPICAL PROPAGATION DELAY 6.0ns TYPICAL SUPPLY CURRENT (TOTAL) 23m A ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F148N N74F148D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS I1 - I7 I0 EI EO GS A0 - A2 DESCRIPTION Priority inputs (active Low) Priority input (active Low) Enable input (active Low) Enable output (active Low) Group select output (active Low) Address outputs (active Low) 74F (U.L.) HIGH/LOW 1.0/2.0 1.0/1.0 1.0/2.0 50/33 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/1.2m A 20µA/0.6m A 20µA/1.2m A...