74F164 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74F164 8-bit serial-in parallel-out shift register Product specification IC15 Data Handbook 1995 Sep 22 Philips Semiconductors Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register Features - Gated serial data inputs - Typical shift frequency of 100MHz - Asynchronous Master Reset - Buffered clock and data inputs - Fully synchronous data transfer - Industrial temperature range available (- 40°C to +85°C) DESCRIPTION The 74F164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered through one of two inputs (Dsa, Dsb); either input can be used as an active High enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied High. Data shifts one place to the right on each Low-to-High transition of the clock (CP) input, and enters into Q0 the logical AND of the two data inputs (Dsa, Dsb) that existed one setup time before the rising edge. A Low level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs Low. PIN CONFIGURATION Dsa Dsb Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 14 VCC 13 Q7 12 Q6 11 Q5 10 Q4 9 8 MR CP SF00717 TYPE 74F164 TYPICAL fmax 100MHz TYPICAL SUPPLY CURRENT (TOTAL) 33m A ORDERING INFORMATION ORDER CODE DESCRIPTION 14-pin plastic DIP 14-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74F164N 74F164D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = - 40°C to +85°C I74F164N I74F164D DRAWING NUMBER SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Dsa, Dsb CP MR Q0 - Q7 Data inputs Clock pulse input (active rising edge) Master reset input (active-Low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low...