74F1763 Datasheet | NXP Semiconductors

FEATURES - DRAM signal timing generator - Automatic refresh circuitry - Selectable row address hold and RAS precharge times - Facilitates page mode accesses - Controls 1 MBit DRAMs - Intelligent burst-mode refresh after page-mode access cycles PRODUCT DESCRIPTION The Philips Semiconductors Intelligent Dynamic RAM Controller is a 1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM Controller. It contains automatic signal timing, address multiplexing and refresh control required for interfacing with dynamic RAMs. Additional features have been added to this device to take advantage of technological advances in Dynamic RAMs. A Page-Mode access pin allows the user to assert RAS for the entire access cycle rather than the pre-defined four-clock-cycle pulse width used for normal random access cycles. In addition, the user has the ability to select the RAS precharge time and Row-Address Hold time to fit the particular DRAMs being used. DTACK has been modified from previous family parts to bee a negative true, tri-stated output. The options for latched or unlatched address are contained on a single device by the addition of an Address Latch Enable (ALE) input. Finally, a burst refresh monitor has been added to ensure plete refreshing after length page-mode access cycles. With a maximum clock frequency of 100 MHz, the F1763 is capable of controlling DRAM arrays with access times down to 40 nsec. TYPICAL SUPPLY CURRENT (TOTAL) 150 m A TYPE 74F1763 f MAX 100 MHz ORDERING INFORMATION PACKAGES 48-pin Plastic DIP MERCIAL RANGE VCC = 5V "10%; TA = 0_C TO 70_C N74F1763N PKG DWG # SOT240-1 INPUT AND OUTPUT LOADING FAN-OUT TABLENO TAG PINS REQ CP PAGE PRECHRG HLDROW DTACK GNT RCP RA0- 9 CA0- 9 ALE RAS CAS MA0- 9 DRAM Request Input Clock Input Page Mode Select Input RAS Precharge Select Input Row Hold Select Input Data Transfer Ack. Output Access Grant Output Refresh Clock Input Row Address Inputs Column Address Inputs Address Latch Enable Input Row Address Strobe Output...