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74HC4060-Q100 - 14-stage binary ripple counter

General Description

The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no.

7A.

They are pin compatible with Low-power Schottky TTL (LSTTL).

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +85 C and from 40 C to +125 C.
  • All active components on chip.
  • RC or crystal oscillator configuration.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ).
  • Multiple package options 3.

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Full PDF Text Transcription for 74HC4060-Q100 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74HC4060-Q100. For precise diagrams, and layout, please refer to the original PDF.

74HC4060-Q100; 74HCT4060-Q100 14-stage binary ripple counter with oscillator Rev. 2 — 10 April 2013 Product data sheet 1. General description The 74HC4060-Q100; 74HCT4060...

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Product data sheet 1. General description The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC4060-Q100; 74HCT4060-Q100 are 14-stage ripple-carry counter/dividers and oscillators with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case kee

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nexperia Logo 74HC4060-Q100 14-stage binary ripple counter nexperia

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