* Input levels:
* For 74HC273: CMOS level
* For 74HCT273: TTL level
* Common clock and master reset
* Eight positive edge-triggered D-type flip-flops
* Complies with JEDEC standard no. 7A
* ESD protection:
* HBM JESD22-A114F exceeds 2000 V
* MM JESD22-A115-A excee
74HCT273 Datasheet (176.16 KB)
74HCT273
176.16 KB
Octal d-type flip-flop.
74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 5 26 February 2016 Product data sheet 1. General descrip.
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