74LVC2G17 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET 74LVC2G17 Dual non-inverting Schmitt-trigger with 5 V tolerant input Product specification Suppersedes data of 2003 Aug 13 2004 Sep 08 Philips Semiconductors Product specification Dual non-inverting Schmitt-trigger with 5 V tolerant input Features - Wide supply voltage range from 1.65 V to 5.5 V - 5 V tolerant input/output for interfacing with 5 V logic - High noise immunity - plies with JEDEC standard: - JESD8-7 (1.65 V to 1.95 V) - JESD8-5 (2.3 V to 2.7 V) - JESD8B/JESD36 (2.7 V to 3.6 V). - ESD protection: - HBM EIA/JESD22-A114-B exceeds 2000 V - MM EIA/JESD22-A115-A exceeds 200 V. - ±24 m A output drive (VCC = 3.0 V) - CMOS low power consumption - Latch-up performance exceeds 250 m A - Direct interface with TTL levels - Multiple package options - Specified from - 40 °C to +85 °C and - 40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL t PHL/t PLH PARAMETER CONDITIONS VCC = 2.5 V; CL = 30 p F; RL = 500 Ω VCC = 2.7 V; CL = 50 p F; RL = 500 Ω VCC = 3.3 V; CL = 50 p F; RL = 500 Ω VCC = 5.0 V; CL = 50 p F; RL = 500 Ω CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in p F; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 DESCRIPTION APPLICATIONS - Wave and pulse shapers for highly noisy environments. The 74LVC2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. These feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using...