triple inverter.
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1..
using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it i.
The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as transl.
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