74LVC544A Datasheet | NXP Semiconductors

Octal D-type registered transceiver; inverting; 3-state Rev. 4 - 18 December 2012 Product data sheet 1. General description The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for each register to permit independent control of input and output in either direction of the data flow. The 74LVC544A contains eight D-type latches, with separate inputs and controls for each set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display the data present at the outputs of the A latches. 2. Features and benefits - 5 V tolerant inputs/outputs for interfacing with 5 V logic - Wide supply voltage range from 1.2 V to 3.6 V - CMOS low-power consumption - Direct interface with TTL levels - 8-bit octal transceiver with D-type latch - Back-to-back registers for storage - Separate controls for data flow in each direction - Supports partial power-down applications; inputs/outputs are high-impedance when VCC = 0 V - plies with JEDEC standard: - JESD8-7A (1.65 V to 1.95 V) - JESD8-5A (2.3 V to 2.7 V) - JESD8-C/JESD36 (2.7 V to 3.6 V) - ESD protection: - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-B exceeds 200 V - CDM JESD22-C101E exceeds 1000 V - Specified from - 40 C to +85 C and - 40 C to +125 C NXP Semiconductors Octal D-type registered transceiver; inverting;...