74LVC646A
description
The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the A or B bus is clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register, or in both. With the select source inputs (SAB and SBA), stored and real-time (transparent mode) data can be multiplexed. The direction (DIR) input determines which bus receives data when OE is active (LOW). In the isolation mode (OE = HIGH), A data may be stored in the B register and/or B data may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit...
