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NXP Semiconductors Electronic Components Datasheet

74LVT16652A Datasheet

3.3V LVT 16-bit bus transceiver/ register 3-State

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INTEGRATED CIRCUITS
74LVT16652A
3.3V LVT 16-bit bus transceiver/ register
(3-State)
Product specification
Supersedes data of 1994
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

74LVT16652A Datasheet

3.3V LVT 16-bit bus transceiver/ register 3-State

No Preview Available !

Philips Semiconductors
3.3V 16-bit bus transceiver/register (3-State)
Product specification
74LVT16652A
FEATURES
16-bit bus interface
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74LVT16652A is a high-performance BiCMOS product
designed for VCC operation at 3.3V. The device can be used as two
8-bit transceivers or one 16-bit transceiver.
Complimentary output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A Low-input level selects real-time data, and a
High input level selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal
flip-flops by Low-to-High transitions at the appropriate clock (CPAB
or CPBA) inputs regardless of the levels on the select-control or
output-enable inputs. When SAB and SBA are in real-time transfer
mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance,
each set of bus lines remains at its last level configuration.
QUICK REFERENCE DATA
SYMBOL
tPLH
tPHL
CIN
CI/O
ICCZ
PARAMETER
Propagation delay
nAx to nBx or nBx to nAx
Input capacitance Control pins
I/O pin capacitance
Total supply current
CONDITIONS
Tamb = 25°C
CL = 50pF;
VCC = 3.3V
VI = 0V or 3.0V
Outputs disabled; VI = 0V or 3.0V
Outputs disabled; VCC = 3.6V
TYPICAL
1.9
3
9
70
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT16652A DL
74LVT16652A DGG
NORTH AMERICA
VT16652A DL
VT16652A DGG
DWG NUMBER
SOT371-1
SOT364-1
LOGIC SYMBOL (IEEE/IEC)
56 EN1(BA)
1 EN2(AB)
55 C3
54 G4
2 C5
3 G6
29 EN7(BA)
28 EN8(AB)
30 C9
31 G10
27 C11
26 G12
5
w1 4 3D
52 15
w1 10 9D
42
1 41
5D 6 w1
7 10 1
11D 12 w1
16 2
6
8
9
10
12
13
14
51 16
49 17
48 19
47 20
45 21
44 23
43 24
1 12 8
41
40
38
37
36
34
33
SW00158
1998 Feb 19
2 853-1767 18986


Part Number 74LVT16652A
Description 3.3V LVT 16-bit bus transceiver/ register 3-State
Maker NXP
Total Page 12 Pages
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