CBTV24DD12A Description
CBTV24DD12A is designed for 1.8 V/2.5 V/3.3 V supply voltage operation and it supports Pseudo Open Drain (POD), SSTL_12, SSTL_15 or SSTL_18 signaling and CMOS select input levels. This device is designed for operation in DDR4, DDR3 or DDR2 memory bus systems, with speeds up to 3200 MT/s. The CBTV24DD12A has a 1.
CBTV24DD12A Key Features
- 12-bit bus width
- 1 : 2 switch/MUX topology
- Bidirectional operation
- Simple CMOS select pins (SEL0, SEL1)
- Simple CMOS enable pin (EN)
- 3200 MT/s throughput
- 7.4 GHz bandwidth (for both single-ended and differential signals)
- Low ON insertion loss
- Low return loss
- Low crosstalk