GTL2000 Datasheet | NXP Semiconductors

FEATURES - 22-bit bi-directional low voltage translator - Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V busses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels - Provides bi-directional voltage translation with no direction pin - Low 6.5 Ω RDSON resistance between input and output pins (Sn/Dn) - Supports hot insertion - No power supply required - Will not latch up - 5 V tolerant inputs - Low stand-by current - Flow-through pinout for ease of printed circuit board trace routing - ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V per JESD22-C101 - Package offer: SSOP48, TSSOP48 APPLICATIONS - Any application that requires bi-directional or unidirectional voltage level translation from any voltage between 1.0 V & 5.0 V to any voltage between 1.0 V & 5.0 V - The open drain construction with no direction pin is ideal for bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I2C port translation to the normal 3.3 V and/or 5.0 V I2C bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels. DESCRIPTION The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2000 provides 22 NMOS pass transistors (Sn and Dn) with a mon gate (GREF) and a reference transistor (SREF and DREF). The device allows bi-directional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is low the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is high, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is high, the Dn port is pulled to VCC by the pull up resistors. This functionality allows a seamless translation between higher and...