HEF4024B Datasheet - NXP

7-stage binary counter

HEF4024B General Description

The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs L.

HEF4024B Datasheet (42.53 KB)

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HEF4024B

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NXP ↗

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42.53 KB

Description:

7-stage binary counter.
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HE.

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HEF4024B 7-stage binary counter NXP

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HEF4024B General Description

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