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JN5142-J01 - JenNet-IP Wireless Microcontroller

Datasheet Summary

Description

2.2.1 Power Supplies 2.2.2 Reset 2.2.3 32MHz Oscillator 2.2.4 Radio 2.2.5 Analogue Peripherals 2.2.6 Digital Input/Output 3 CPU 4 Memory Organisation 4.1 ROM 4.2 RAM 4.3 OTP eFuse Memory 4.4 External Memory 4.4.1 External Memory Encryption 4.5 Peripherals 4.6 Internal Non-Volatile Memory (NVM) 4.7

Features

  • an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver, 128KB of ROM, 32KB of RAM, and a comprehensive mix of analogue and digital peripherals. The JenNet-IP network stack is embedded in the device ROM. The operating current is below 18mA, allowing operation direct from a coin cell. The peripherals.

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Datasheet Details

Part number JN5142-J01
Manufacturer NXP
File Size 915.70 KB
Description JenNet-IP Wireless Microcontroller
Datasheet download datasheet JN5142-J01 Datasheet
Additional preview pages of the JN5142-J01 datasheet.

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Full PDF Text Transcription

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Data Sheet: JN5142-J01 JenNet-IP Wireless Microcontroller Overview The JN5142-J01 is an ultra low power, high performance wireless microcontroller suitable for use in JenNet-IP Smart Devices. The JN5142 features an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver, 128KB of ROM, 32KB of RAM, and a comprehensive mix of analogue and digital peripherals. The JenNet-IP network stack is embedded in the device ROM. The operating current is below 18mA, allowing operation direct from a coin cell. The peripherals support a wide range of applications.
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