NXP Semiconductors
IEEE 802.15.4 low power wireless
JN5189
2.2 Radio features
2.4 GHz IEEE 802.15.4 2011 compliant
Receiver current 4.3 mA
IEEE 802.15.4 Receiver sensitivity 100 dBm
Improved co-existence with WiFi
Configurable transmit power up to +11 dBm, with 46 dB range
Transmit power / current +10 dBm / 20.28 mA
Transmit power / current +3 dBm / 9.44 mA
Transmit power / current 0 dBm / 7.36 mA
1.9 V to 3.6 V supply voltage
Antenna Diversity control
32 MHz XTAL cell with internal capacitors, able with suitable external XTAL to meet
the required accuracy for radio operation over the operating conditions
Integrated RF balun
Integrated ultra Low-power sleep oscillator
Deep Power-down current 350 nA (with wake-up from IO)
128-bit or 256-bit AES security processor
MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers
2.3 Microcontroller features
Application CPU, Arm Cortex-M4 CPUs:
Arm Cortex-M4 processor, running at a frequency of up to 48 MHz.
Arm built-in Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit (MPU)
Non-maskable Interrupt (NMI) with a selection of sources
Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints
System tick timer
Includes Serial Wire Output for enhanced debug capabilities.
On-Chip memory
640 KB flash (320 KB for JN5188)
152 KB SRAM (88 KB for JN5188)
12 MHz to 48 MHz system clock speed for low-power
2 x I2C-bus interface, operate as either master or slave
10 x PWM
2 x Low-power timers
2 x USART, one with flow control
2 x SPI-bus, master or slave
1 x PDM digital audio interface with a hardware based voice activity detector to reduce
power consumption in voice applications. Support for dual-channel microphone
interface, flexible decimators, 16 entry FIFOs and optional DC blocking.
19-channel DMA engine for efficient data transfer between peripherals and SRAM, or
SRAM to SRAM. DMA can operate with fixed or incrementing addresses. Operations
can be chained together to provide complex functionality with low CPU overhead.
JN5189
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 22 February 2020
© NXP B.V. 2020. All rights reserved.
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