MC68HC705SP7 Datasheet | NXP Semiconductors

Description General reformat to bring document up to current publication standards References to MC68HRC705SJ7 and MC68HRC705SP7 removed throughout Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit - Change label of register $1FF0 from mask option register to COP register Table 7-2. Port B Pin Functions - PB0- PB4 - Change heading under parator 1 from OPT in MOR to OPT in COPR 12.4 PEPROM Programming - Contact information updated Figure 13-3. EPROM Security in COP and Security Register (COPR) - Figure title change 13.4 EPROM Programming - Contact information updated and corrected reference to COP register from COP to COPR 15.15 SIOP Timing (VDD = 5.0 Vdc) - Value change for clock (SCK) low time 15.16 SIOP Timing (VDD = 3.0 Vdc) - Value change for clock (SCK) low time Section 15. Electrical Specifications - Added Figure 15-1 through Figure 15-10 and Figure 15-12 September, 2005 Updated to meet Freescale identity guidelines. Page Number(s) All All 96 179 188 226 213, 214, 219, 223, and 227 Throughout MC68HC705JJ7 - MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor List of Chapters Chapter 1 General Description - - - - - -...