MC9S08PT16 Datasheet | NXP Semiconductors

features - 8-Bit S08 central processor unit (CPU) - Up to 20 MHz bus at 2.7 V to 5.5 V across temperature range of -40 °C to 105 °C - Supporting up to 40 interrupt/reset sources - Supporting up to four-level nested interrupt - On-chip memory - Up to 16 KB flash read/program/erase over full operating voltage and temperature - Up to 256 byte EEPROM; 2-byte erase sector; program and erase while executing flash - Up to 2048 byte random-access memory (RAM) - Flash and RAM access protection - Power-saving modes - One low-power stop mode; reduced power wait mode - Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode - Clocks - Oscillator (XOSC) - loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 k Hz to 39.0625 k Hz or 4 MHz to 20 MHz - Internal clock source (ICS) - containing a frequencylocked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 2% deviation across the whole operating temperature; up to 20 MHz - System protection - Watchdog with independent clock source - Low-voltage detection with reset or interrupt; selectable trip points - Illegal opcode detection with reset - Illegal address detection with reset MC9S08PT16A and MC9S08PT8A are remended for new design - Development support - Single-wire background debug interface - Breakpoint capability to allow three breakpoints setting during in-circuit debugging - On-chip in-circuit emulator (ICE) debug module containing two parators and nine trigger modes - Peripherals - ACMP - one analog parator with both positive and negative inputs; separately selectable interrupt on rising and falling parator output; filtering - ADC - 12-channel, 12-bit resolution; 2.5 µs conversion time; data buffers with optional watermark; automatic pare function; internal bandgap...