MCIMX537CVV8C
Description
Multilevel memory system-The multilevel memory system of the i.MX53 is based on the L1 instruction and data caches, L2 cache, internal and external memory.
Key Features
- ARM Cortex™-A8 core, which operates at clock speeds as high as 800 MHz
- The flexibility of the i.MX53 architecture allows for its use in a wide variety of applications
- Features of the i.MX53 processor include the following
Applications
- Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Functional Part Differences and - Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1. - Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1. Special Signal Considerations . . . . . . . . . . . . . . . 16
