MIMX8MM1CVTKZAA
Key Features
- Features Features Quad symmetric Cortex-A53 processors
- 32 KB L1 Instruction Cache
- 32 KB L1 Data Cache
- Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data architecture:
- Floating Point Unit (FPU) with support of the VFPv4-D16 architecture Support of 64-bit Armv8-A architecture 512 KB unified L2 cache Low power microcontroller available for customer application:
- low power standby mode
- IoT features including Weave
- Manage IR or Wireless Remote Cortex M4 CPU:
- 16 KB L1 Instruction Cache
- 16 KB L1 Data Cache
