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MIMX8MQ5CVAHZAA - Applications Processors

This page provides the datasheet information for the MIMX8MQ5CVAHZAA, a member of the MIMX8MQ7CVAHZAA Applications Processors family.

Features

  • Feature Quad symmetric Cortex-A53 processors:.
  • 32 KB L1 Instruction Cache.
  • 32 KB L1 Data Cache.
  • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture:.
  • 1 MB unified L2 cache.
  • Support L2 cache RAMs protection with ECC.
  • Frequency of 1.5 GHz 16 KB L1 Instruction Cache 16 KB L1 Data Cache 256 KB tightly coupled memory (TCM) Two PCI Express Gen2 interfaces Two USB 3.0/2.0 controllers with integrated PHY interfaces.

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Other Datasheets by NXP

Full PDF Text Transcription

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NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8MDQLQIEC Rev. 3, 04/2021 MIMX8MQ6CVAHZAA MIMX8MD6CVAHZAA MIMX8MQ5CVAHZAA MIMX8MQ6CVAHZAB MIMX8MD6CVAHZAB MIMX8MQ5CVAHZAB i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products Package Information Bare Die Package FBGA 17 x 17 mm, 0.65 mm pitch Ordering Information See Table 2 on page 6 1 i.MX 8M Dual / 8M QuadLite / 8M Quad introduction The i.MX 8M Dual / 8M QuadLite / 8M Quad processors 1. i.MX 8M Dual / 8M QuadLite / 8M Quad introduction . . . 1 represent NXP’s latest market of connected streaming 1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 audio/video devices, scanning/imaging devices, and 2. 1.2. Ordering information . . . . . . . .
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