Secure smart card controller
2. General description
2.1 General remarks
This document offers an introduction into the features and the architecture of the
SmartMX2 P40 products.
The product data sheet and other detailed documentation, e.g. for Card Operating System
(COS) development are available through NXP’s portal for secured documentation.
Access to such documents is granted on a need-to-know basis. Contact NXP sales for
registration and access.
2.2 Naming conventions
Table 2. Naming conventions
Interface and feature configuration identifier, as currently defined, e.g.:
x = C:
Asymmetric and symmetric cryptography implemented, ISO/IEC 7816
Indication of the Non-Volatile memory size in KB
eee = 012: 13 KB EEPROM implemented
eee = 040: 40 KB EEPROM implemented
eee = 072: 72 KB EEPROM implemented
2.3 Contact interfaces
Operating in accordance with ISO/IEC 7816, the SmartMX2 P40 contact interface is
supported by a built-in Universal Asynchronous Receiver/Transmitter (UART). P40 UART
enables data rates of up to 688 kbit/s allowing for the automatic generation of all typical
baud rates and supports transmission protocols T=0 and T=1.
2.4 Public Key Crypto (PKC) coprocessor
The PKCC is speeding up the computation of public-key cryptographic operations within
The PKC coprocessor flexible interface provides programmers with the freedom to
implement their own cryptographic algorithms. A Common Criteria certified crypto library
from NXP providing a large range of required functions is available for all devices listed in
Table 4 in order to support customers in implementing public key-based solutions.
2.5 Coprocessor for DES and AES
The DES algorithm, widely used for symmetric encryption, is supported by a dedicated,
high performance, highly attack-resistant hardware coprocessor. Relevant standards
(ISO/IEC, ANSI, FIPS) are fully supported. A secure crypto library element for DES is
The same coprocessor supports secure AES as well. The implementation is based on
FIPS197 as standardized by the National Institute for Standards and Technology (NIST),
for key lengths of 128-bit, 192-bit, and 256-bit with performance levels comparable to
Product short data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 24 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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