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NXP Semiconductors Electronic Components Datasheet

PCU9661 Datasheet

Parallel bus to 1 channel UFm I2C-bus controller

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PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
Rev. 1 — 12 September 2011
Product data sheet
1. General description
The PCU9661 is an advanced single master mode I2C-bus controller. It is a fourth
generation bus controller designed for data intensive I2C-bus data transfers. It has a
transmit only transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus
with push-pull topology. The serial channel has a generous 4352 byte data buffer which
makes the PCU9661 the ideal companion to any CPU that needs to transmit and receive
large amounts of serial data with minimal interruptions.
The PCU9661 is an 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to
communicate with up to 64 slaves in one serial sequence with no intervention from the
CPU. The controller also has a sequence loop control feature that allows it to
automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level.
A simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface
5 Mbit/s unidirectional data transfer Ultra Fast-mode (UFm) channel (push-pull driver)
Internal oscillator trimmed to 1 % accuracy reduces external components
4352-byte UFm channel buffer
Three levels of reset: software channel reset, global software reset on parallel bus,
global hardware RESET pin
Communicates with up to 64 slaves in one serial sequence
Sequence looping with interval timer
JTAG port available for boundary scan testing during board manufacturing process
Trigger input synchronizes serial communication exactly with external events
Maskable interrupts
Operating supply voltage: 3.0 V to 3.6 V (device and host interface)


NXP Semiconductors Electronic Components Datasheet

PCU9661 Datasheet

Parallel bus to 1 channel UFm I2C-bus controller

No Preview Available !

NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
I2C-bus I/O supply voltage: 3.0 V to 5.5 V
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
ESD protection exceeds 8000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: LQFP48
3. Applications
Add UFm I2C-bus port to controllers/processors that do not have one
Add additional UFm I2C-bus ports to controllers/processors that need multiple I2C-bus
ports
Converts 8 bits of parallel data to serial data stream to prevent having to run a large
number of traces across the entire printed-circuit board
Entertainment systems
LED matrix control
Data intensive I2C-bus transfers
4. Ordering information
Table 1. Ordering information
Type number Topside
mark
Package
Name
PCU9661B
PCU9661 LQFP48
Description
plastic low profile quad flat package;
48 leads; body 7 7 1.4 mm
Version
SOT313-2
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
2 of 52


Part Number PCU9661
Description Parallel bus to 1 channel UFm I2C-bus controller
Maker NXP
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PCU9661 Datasheet PDF






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