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NXP Semiconductors Electronic Components Datasheet

PLC42VA12 Datasheet

CMOS programmable multi-function PLD 42 x 105 x 12

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Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
DESCRIPTION
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
advantages and none of the disadvantages
associated with the “V” type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
The most significant improvement in the
Output Macro Cell structure is the
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other “V” type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
FEATURES
High-speed EPROM-based CMOS
Multi-Function PLD
Super set of 22V10, 32VX10 and
20RA10 PAL® ICs
Two fully programmable arrays eliminate
“P-term Depletion”
Up to 64 P-terms per OR function
Improved Output Macro Cell Structure
Individually programmable as:
* Registered Output with feedback
* Registered Input
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
Bypassed Registers are 100% functional
with separate input and feedback paths
Individual Output Enable control
functions
* From pin or AND array
Reprogrammable – 100% tested for
programmability
Eleven clock sources
Register Preload and Diagnostic Test Mode
Features
Security fuse
APPLICATIONS
Mealy or Moore State Machines
Synchronous
Asynchronous
Multiple, independent State Machines
10-bit ripple cascade
Sequence recognition
Bus Protocol generation
Industrial control
A/D Scanning
PIN CONFIGURATIONS
FA and N Pack-
ages
I0/CLK 1
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
I8 9
B0 10
B1 11
GND 12
24 VCC
23 M9
22 M8
21 M7
20 M6
19 M5
18 M4
17 M3
16 M2
15 M1
14 M0
13 I9/OE
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
A Package
I0/
I2 I1 CLK N/C VCC M9 M8
4 3 2 1 28 27 26
I3 5
25 M7
I4 6
24 M6
I5 7
23 M5
N/C 8
22 N/C
I6 9
21 M4
I7 10
20 M3
I8 11
19 M2
12 13 14 15 16 17 18
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
ORDER CODE
PLC42VA12FA
PLC42VA12N
PLC42VA12A
DRAWING NUMBER
1478A
0410D
0401F
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993
73
853–1414 11164


NXP Semiconductors Electronic Components Datasheet

PLC42VA12 Datasheet

CMOS programmable multi-function PLD 42 x 105 x 12

No Preview Available !

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
LOGIC DIAGRAM
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 FC
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
I8 9
RRRR C
PMMMM K
A8 7 6 5 8
PR
J CK
KQ
PR
J CK
KQ
PR
J CK
KQ
JPCRK
KQ
NOTE:
Programmable
Connection
October 22, 1993
74


Part Number PLC42VA12
Description CMOS programmable multi-function PLD 42 x 105 x 12
Maker NXP
Total Page 20 Pages
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