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PTN3363 Datasheet

Low power HDMI/DVI level shifter

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PTN3363
Low power HDMI/DVI level shifter with active DDC buffer,
supporting 3.4 Gbit/s operation
Rev. 1 — 12 August 2014
Product data sheet
1. General description
PTN3363 is a low power, high-speed level shifter device which converts four lanes of
low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant
open-drain current-steering differential output signals, up to 3.4 Gbit/s per lane to support
36-bit deep color mode, 4K 2K video format or 3D video data transport. Each of these
lanes provides a level-shifting differential active buffer, with built-in Equalization, to
translate from low-swing AC-coupled differential signaling on the source side, to
TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V
on the sink side. Additionally, the PTN3363 provides a single-ended active buffer for
voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side
and provides a channel with active buffering and level shifting of the DDC channel
(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The
DDC channel is implemented using active I2C-bus buffer technology providing redriving
and level shifting as well as disablement (isolation between source and sink) of the clock
and data lines.
The low-swing AC-coupled differential input signals to the PTN3363 typically come from a
display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3363, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure 1.
The PTN3363 main high-speed differential lanes feature low-swing self-biasing differential
inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2a
and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs
compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The I2C-bus channel
actively buffers as well as level-translates the DDC signals. The PTN3363 supports
standby mode in order to minimize current consumption when Hot Plug Detect signal
HPD_SINK is LOW.
PTN3363 is powered from a single 3.3 V power supply consuming a small amount of
power (72 mW typical) and is offered in a 32-terminal HVQFN32 package.


NXP Semiconductors Electronic Components Datasheet

PTN3363 Datasheet

Low power HDMI/DVI level shifter

No Preview Available !

NXP Semiconductors
PTN3363
Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation
MULTI-MODE DISPLAY SOURCE
DP PHY ELECTRICAL
TMDS
DP
coded
output buffer
data TX
FF
TX
TMDS
DP
coded
output buffer
data TX
FF
TX
TMDS
DP
coded
output buffer
data TX
FF
TX
TMDS
DP
clock
output buffer
pattern TX
FF
TX
CONFIGURATION
DDC I/O
(I2C-bus)
OE_N
reconfigurable I/Os
PTN3363
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D4+
IN_D4
OUT_D4+
OUT_D4
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D3+
IN_D3
OUT_D3+
OUT_D3
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D2+
IN_D2
OUT_D2+
OUT_D2
AC-coupled
differential pair
clock
CLOCK LANE
IN_D1+
IN_D1
OUT_D1+
OUT_D1
0 V to 3.3 V
HPD_SOURCE
binary inputs EQ0/EQ1
3.3 V DDC_EN
3.3 V 3.3 V
DDET
0 V to 5 V
HPD_SINK
5V
3.3 V
SCL_SOURCE
SCL_SINK
5V
SDA_SOURCE
SDA_SINK
HIZ_EN
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to IN_D[4:1].
Fig 1. Typical HDMI/DVI level shifter application system diagram
002aah235
PTN3363
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 August 2014
© NXP B.V. 2014. All rights reserved.
2 of 30


Part Number PTN3363
Description Low power HDMI/DVI level shifter
Maker NXP
Total Page 3 Pages
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