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NXP Semiconductors Electronic Components Datasheet

SAC57D54H Datasheet

CPU

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NXP Semiconductors
Data Sheet: Technical Data
Document Number SAC57D54H
Rev. 7, 05/2017
SAC57D54H
Features
• ARM™ Cortex-A5, 32-bit CPU
– Supports ARMv7- ISA
– 32 KB Instruction cache, 32 KB Data cache
– NEON SIMD Media Processing Engine
– FPU supporting double precision floating point
operations
– Memory Management Unit
– GIC Interrupt Controller
– Up to 320 MHz
• ARM™ Cortex-M4, 32-bit CPU
– Supports ARMv7 - ISA
– 16 KB Instruction cache, 16 KB Data cache
– 64 KB Tightly-Coupled Memory (TCM)
– Single Precision FPU
– NVIC Interrupts Controller
– 1.25 DMIPS per MHz integer performance
– Up to 160 MHz
• I/O Processor
– ARM™ Cortex-M0+, 32-bit CPU
– Intelligent Stepper Motor Drive
SAC57D54H
• Debug functionality
– Run-time debug control of cores and visibility of
system resources using the Debug Access Port
(DAP)
– IEEE 1149.1/ IEEE 1149.7 System JTAG Controller
(SJTAG)
– Program and Data Trace support (16-bit data width)
implemented by the ARM Trace Port Interface Unit
(TPIU) Trace capture
• Timer
– Four 8-channel Flextimer modules (FTM)
– Two 4 channel System Timer Module (STM)
– Three Software WatchDog Timers (SWT)
– One 8 channel Periodic Interrupt Timer (PIT)
– Autonomous Real Time Counter (RTC)
• Analog
– 1 x 24 channel, 12-bit analog-to-digital converter
(ADC)
– 2 analog comparators (CMP)
• Security
– Cryptographic Services Engine (CSE)
• Memory subsystem
– System Memory Protection Unit
– 4 MB on-chip flash supported with the flash
controller
– 1 MB on-chip SRAM with ECC
– 1.3 MB on-chip Graphics SRAM with FlexECC
• Safety
– ISO26262 ASIL-B compliance
– Password and Device Security (PASS) supporting
advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to
collect faults and issue interrupts
• Supports wake-up from low power modes via the
WKPU controller
• Multiple operating modes
– Includes enhanced low power operation
• On-chip voltage regulator
– External 3.3 V input supply
– Option for direct, external supply of core voltage
– Low Voltage Detect (LVD) and High Voltage
Detect (HVD) on various supplies and regulators
• Memory interfaces
– 2 x Dual QuadSPI Serial flash controllers
– Supports SDR and DDR serial flash
– Support for 3.3 V Hyperflash (Spansion)
– DRAM controller supporting SDR and DDR2
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 kHz IRC (SIRC)
– 32 kHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.


NXP Semiconductors Electronic Components Datasheet

SAC57D54H Datasheet

CPU

No Preview Available !

• Graphics interfaces
– Vivante GC355 GPU supporting OpenVG 1.1
– 2 x 2D-ACE Display Controllers (with inline Head-Up-Display warping)
– Digital RGB, TCON_0 (RSDS), TCON_1 and OpenLDI/LVDS output options
– Digital Video Input (VIU4)
– RLE Decoder for memory-memory decompression
– 40x4 segment LCD driver, reconfigurable as 38x6 or 36x8
• Cluster peripherals
– Sound Generator Module (SGM)
– 6 Stepper Motor Drivers with Stepper Stall Detect
• Communication
– Ethernet 10/100 + AVB (ENET)
– MLB50
– FlexCAN x 3
– DSPI x 5
– LINFlexD x 3 (1 x Master/Slave, 2 x Master only)
– I2C x 2
• eDMA controller with multiple transfer request sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flash programming
SAC57D54H, Rev. 7, 05/2017
2
NXP Semiconductors


Part Number SAC57D54H
Description CPU
Maker NXP
Total Page 3 Pages
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