TDA9151B Datasheet | NXP Semiconductors

FEATURES General - 6.75, 13.5 and 27 MHz clock frequency - Few external ponents - Synchronous logic - I2C-bus controlled - Easy interfacing - Low power - ESD protection - Flash detection with restart - Two-level sandcastle pulse. Vertical deflection - 16-bit precision vertical scan - Self adaptive or programmable fixed slope mode - DC coupled deflection to prevent picture bounce - Programmable fixed pression to 75% - Programmable vertical expansion in the fixed slope mode - S-correction can be preset - S-correction setting independent of the field frequency - Differential output for high DC stability - Current source outputs for high EMC immunity - Programmable de-interlace phase. East-West correction - DC coupled EW correction to prevent picture bounce - 2nd and 4th order geometry correction can be preset - Trapezium correction - Geometry correction settings are independent of field frequency - Self adaptive Bult generator prevents ringing of the horizontal deflection - Current source output for high EMC immunity. ORDERING INFORMATION PACKAGE TYPE NUMBER PINS TDA9151B 20 PIN POSITION DIP MATERIAL plastic EHT correction Horizontal deflection - Phase 2 loop with low jitter - Internal loop filter - Dual slicer horizontal flyback input - Soft start by I2C-bus - Over voltage protection/detection with selection and status bit. - Input selection between aquadag or EHT bleeder - Internal filter. GENERAL DESCRIPTION The TDA9151B is a programmable deflection controller contained in a 20-pin DIP package and constructed using BIMOS technology. This high performance synchronization and DC deflection processor has been especially designed for use in both digital and analog based TV receivers and monitors, and serves horizontal and vertical deflection functions for all TV standards. The TDA9151B uses a line-locked clock at 6.75, 13.5 or 27 MHz, depending on the line frequency and application, and requires only a few external ponents. The device can be programmed in a...