ADC1610S Key Features
- SNR, 72.5 dBFS; SFDR, 88 dBc Sample rate up to 125 Msps 16-bit pipelined ADC core Clock input divider by 2 for less jitt
- Single 3 V supply
- Flexible input voltage range: 1 V to 2 V (peak-to-peak)
- CMOS or LVDS DDR digital outputs
- Power-down and Sleep modes
- Input bandwidth, 600 MHz Power dissipation, 430 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer
- Fast OuT of Range (OTR) detection
- INL ±1 LSB, DNL ±0.5 LSB
- Offset binary, two’s plement, gray code
- HVQFN40 package