* I I I I I I I I I I Dual 10-bit resolution Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz Input data rate up to 80 MHz 2 × interpolation filter Output data rate up to 160 Mhz Single 3.3 V power supply Low noise capacitor free integrated Phase-Locked Loop (PLL) Low power dissipation HTQFP80 pa
DAC1003D160 Datasheet (148.12 KB)
DAC1003D160
NXP ↗ Semiconductors
148.12 KB
Dual 10 bits dac.
DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Rev. 02 13 August 2008 www.DataSheet4U.com Product data sheet 1. General d.
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