LPC1769 Key Features
- Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)
- Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator
- In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
- On-chip SRAM includes
- 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access
- Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet,
- Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UA
- Multilayer AHB matrix interconnect provides a separate bus for each AHB master. A