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PCKEL14 Datasheet

2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip

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PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Rev. 01 — 14 October 2002
Product data
1. Description
The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low
skew clock distribution applications. The device can be driven by either a differential
or single-ended ECL, or if positive power supplies are used, PECL input signal. The
PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of
2.375 V to 3.8 V (or 2.375 V to 3.8 V).
The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower
speed scan or test clock along with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor), the SEL pin will select the
differential clock input.
The common enable (EN) is synchronous, so that the outputs will only be
enabled/disabled when they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled, as can happen
with an asynchronous control. The internal flip-flop is clocked on the falling edge of
the input clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The VBB pin (an internally generated voltage supply) is available to this device only.
For single-ended conditions, the unused differential input is connected to VBB as a
switching reference voltage. VBB may also rebias AC-coupled inputs. When used,
decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to
0.1 mA. When not used, VBB should be left open.
2. Features
s 50 ps output-to-output skew at 3.3 V
s Synchronous enable/disable
s Multiplexed clock input
s ESD protection: > 2.5 kV HBM
s The PCK series contains temperature compensation
s PECL mode operating range: VCC = 2.375 V to 3.8 V, with VEE = 0 V
s NECL mode operating range: VCC = 0 V, with VEE = 2.375 V to 3.8 V
s Internal 75 kpull-down resistors on all inputs, plus a 37.5 kpull-up on CLK
s Q output will default LOW with inputs open or at VEE
s Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test
s Moisture sensitivity level 1
s Flammability rating: UL-94 code V-0 @ 1/8”
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NXP Semiconductors Electronic Components Datasheet

PCKEL14 Datasheet

2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip

No Preview Available !

www.DataSheet.co.kr
Philips Semiconductors
3. Pinning information
3.1 Pinning
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 6
Q3 7
Q3 8
Q4 9
Q4 10
20 VCC
19 EN
18 VCC
17 NC
16 SCLK
15 CLK
14 CLK
13 VBB
12 SEL
11 VEE
002aaa217
Fig 1. SO20 pin configuration.
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 6
Q3 7
Q3 8
Q4 9
Q4 10
20 VCC
19 EN
18 VCC
17 NC
16 SCLK
15 CLK
14 CLK
13 VBB
12 SEL
11 VEE
002aaa353
Fig 2. TSSOP pin configuration.
3.2 Pin description
Table 1:
Symbol
Q0-Q4
Q0-Q4
VEE
SEL
VBB
CLK
CLK
SCLK
NC
EN
VCC
Pin description
Pin
1, 3, 5, 7, 9
2, 4, 6, 8, 10
11
12
13
14
15
16
17
19
18, 20
Description
ECL differential clock outputs, non-inverted
ECL differential clock outputs, inverted
negative supply voltage
ECL clock select input
reference voltage output
ECL differential clock input, inverted
ECL differential clock input, non-inverted
ECL scan clock input
no connect
ECL synchronous enable, Active-LOW
positive supply voltage
3.2.1 Power supply connection
CAUTION
All VCC and VEE pins must be connected to an appropriate power
supply to guarantee proper operation.
MSC895
9397 750 09564
Product data
Rev. 01 — 14 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
2 of 15
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Part Number PCKEL14
Description 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Maker NXP Semiconductors
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