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PH2520U Datasheet

N-channel TrenchMOS ultra low level FET

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PH2520U
N-channel TrenchMOS ultra low level FET
Rev. 03 — 2 March 2009
Product data sheet
1. Product profile
1.1 General description
Ultra low level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Higher operating power due to low
thermal resistance
„ Interfaces directly with low voltage
gate drivers
„ Low conduction losses due to low
on-state resistance
1.3 Applications
„ DC-to-DC convertors
„ Notebook computers
„ Portable equipment
„ Switched-mode power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS drain-source voltage Tj 25 °C; Tj 150 °C
ID drain current
Tmb = 25 °C; VGS = 4.5 V;
see Figure 1; see Figure 3
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 50 A;
VDS = 10 V; Tj = 25 °C;
see Figure 11; see Figure 12
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 4.5 V; ID = 25 A;
Tj = 25 °C; see Figure 9;
see Figure 10
Min Typ Max Unit
- - 20 V
- - 100 A
- - 62.5 W
- 18 - nC
- 2.1 2.7 m


NXP Semiconductors Electronic Components Datasheet

PH2520U Datasheet

N-channel TrenchMOS ultra low level FET

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NXP Semiconductors
PH2520U
N-channel TrenchMOS ultra low level FET
2. Pinning information
Table 2. Pinning information
Pin Symbol Description
1S
source
2S
source
3S
source
4G
gate
mb D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
1234
SOT669
(LFPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PH2520U
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
4. Limiting values
Version
SOT669
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
VDGR
VGS
ID
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
Conditions
Tj 25 °C; Tj 150 °C
Tj 25 °C; Tj 150 °C; RGS = 20 k
VGS = 4.5 V; Tmb = 100 °C; see Figure 1
VGS = 4.5 V; Tmb = 25 °C; see Figure 1;
see Figure 3
tp 10 µs; pulsed; Tmb = 25 °C; see Figure 3
Tmb = 25 °C; see Figure 2
IS source current Tmb = 25 °C
ISM peak source current tp 10 µs; pulsed; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj = 25 °C; ID = 70.7 A; RGS = 50 ;
drain-source avalanche Vsup 20 V; tp = 0.1 ms; unclamped
energy
Min Max Unit
- 20 V
- 20 V
-10 10
V
- 73 A
- 100 A
- 300 A
- 62.5 W
-55 150 °C
-55 150 °C
- 52 A
- 150 A
- 250 mJ
PH2520U_3
Product data sheet
Rev. 03 — 2 March 2009
© NXP B.V. 2009. All rights reserved.
2 of 12


Part Number PH2520U
Description N-channel TrenchMOS ultra low level FET
Maker NXP Semiconductors
Total Page 12 Pages
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