N16T1618C2A Datasheet | NanoAmp Solutions

Overview The N16T1618C2(D1/A1)A is an integrated memory device containing a 16 Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 1,048,576 words by 16 bits. It is designed to be patible in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. The device is available in a 2 CE (chip enable) version and two ZZ (deep sleep) versions. The ZZ version includes several power saving modes: a deep sleep mode where data is not retained in the array and partial array refresh mode where data is retained in a portion of the array. Both these modes reduce standby current drain. The VFBGA package has separate power rails, Vcc Q and Vss Q for the I/O to be run from a separate power supply from the device core. Features - Dual voltage for Optimum Performance VCCQ and VSSQ for separate I/O power rails Vcc - 1.65V to 2.2 V Vccq - 1.65V to 3.6V - Fast Cycle Times TACC < 85 n S - Very low standby current ISB < 40µA @ 1.8V - Very low operating current Icc < 25m A - Memory expansion with CE and OE - Automatic power down mode - 48-Pin VFBGA, Wafers Available Product Family Part Number N16T1618C2AZ N16T1618D1AZ N16T1618A1AZ Feature 2 CE Deep Sleep Disabled Deep Sleep Active Package Operating Type Temperature Power Supply Speed Standby Current (ISB), Max 40 µA @ 1.8V Operating Current (Icc), Max - BGA -30o C to +85o C 1.65V - 2.2V 85ns @ 1.65V 3 m A @ 1MHz Pin Configuration 1 A B C D E F G H LB I/O8 I/O9 Pin Descriptions A0 A3 A5 A17 OE UB I/O10 A1 A4 A6 A7 A16 A15 A13...