Description
The 2Gb Double-Data-Rate-3 (DDR3(L)) H-die DRAM is double data rate architecture to achieve high-speed operation.
Features
- and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in BGA packages. 3
REV 1.4
02 /2013
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NT5CB128M16HP-Nanya.pdf
