NT5CC512M8CN, NT5CB512M8CN - Industrial and Automotive DDR3(L) 4Gb SDRAM

Nanya

Datasheet Details

Part number	NT5CC512M8CN, NT5CB512M8CN
Manufacturer	Nanya
File Size	3.88 MB
Description	Industrial and Automotive DDR3(L) 4Gb SDRAM
Datasheet	NT5CB512M8CN-Nanya.pdf
Note	This datasheet PDF includes multiple part numbers: NT5CC512M8CN, NT5CB512M8CN. Please refer to the document for exact specifications by model.

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits.

JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/ ) - Double-data rate on DQs, DQS and DM.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Signal Synchronization - Write Leveling via MR settings -.

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Published: Mar 24, 2014 |