NT5CC512M8CN sdram equivalent, industrial and automotive ddr3(l) 4gb sdram.
* JEDEC DDR3 Compliant
- 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/ ) - Double-data rate on DQs, DQS and DM
* Signal Integrity
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The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are syn.
The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM. The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchron.
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