NT5CC64M16FP Datasheet, Nanya

* JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
* Data Integrity - A.

The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are syn.

The 1Gb Double-Data-Rate-3 (DDR3(L)) F-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank .