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NT5DS64M4AT - (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM

Download the NT5DS64M4AT datasheet PDF. This datasheet also covers the NT5DS32M8AT variant, as both devices belong to the same (nt5dsxxmxax) 256mb ddr333/300 sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

It is internally configured as a quad-bank DRAM.

The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations.

Key Features

  • CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz).
  • DDR333 (-6) DDR300 (-66) 133 133 166 150.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is centeraligned with data for writes.
  • Differential clock inputs (CK and CK).
  • Four internal banks for.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NT5DS32M8AT_Nanya.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NT5DS64M4AT
Manufacturer Nanya
File Size 569.21 KB
Description (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM
Datasheet download datasheet NT5DS64M4AT Datasheet

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NT5DS64M4BS (NT5DSxxMxBx) 256Mb DDR SDRAM Nanya Techology
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Other Datasheets by Nanya

Part Number Description
NT5DS64M4AW (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM
NT5DS16M16ES Commercial and Industrial Consumer DDR 256Mb SDRAM
NT5DS32M8AT 256Mb DDR333/300 SDRAM
NT5DS32M8AW (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM
NT5DS32M8ES Commercial and Industrial Consumer DDR 256Mb SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333/300 SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz)* DDR333 (-6) DDR300 (-66) 133 133 166 150 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions.