Description
Symbol
Type
CK, CK
Input
CKE
Input
CS Input
RAS, CAS,WE
Input
DM (LDM, UDM)
Input
BA0
BA2
Input
A0
A13
Input
Function
Clock: CK and CK are differential clock inputs.All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and
Features
- JEDEC DDR2 Compliant - Double-data rate on DQs, DQS, DM bus - 4n Prefetch Architecture.
- Throughput of valid Commands - Posted CAS and Additive Latency (AL).
- Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination.
- Data Integrity - Auto Refresh and Self Refresh Modes.
- Power Saving Modes - Power Down Mode - Partial Array Self Refresh (PASR).
- SSTL_18 compliance and Power Supply - VDD/VDDQ = 1.70 to 1.90V
Options.
- Speed Gr.