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NT4GC72B8PB0NL Datasheet Preview

NT4GC72B8PB0NL Datasheet

Registered DDR3 SDRAM DIMM

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NT2GC72B89B0NJ/NT2GC72B89B2NJ/NT2GC72C89B0NJ/NT2GC72C89B2NJ
NT4GC72B4PB0NL/NT4GC72C4PB0NL/NT4GC72C4PB2NL/NT4GC72B8PB0NL/NT4GC72C8PB0NL/NT4GC72C8PB2NL
NT8GC72B4NB1NJ/NT8GC72B4NB3NJ/NT8GC72C4NB1NJ/NT8GC72C4NB3NJ
NT16TC72B4NB1NL/NT16TC72C4NB1NL/NT16TC72C4NB3NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 / 16GB: 2G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
Based on DDR3-1066/1333 256Mx8 (2GB/4GB) / 512Mx4 (4GB/8GB) SDRAM B-Die
Based on DDR3-1066 1Gx4 (DDP) (16GB) SDRAM B-Die
Features
•Performance:
Speed Sort
PC3-8500 PC3-10600
-BE -CG Unit
DIMM CAS Latency
79
fck Clock Frequency
533 667 MHz
tck Clock Cycle
1.875
1.5 ns
fDQ DQ Burst Frequency 1066
1333
Mbps
240-Pin Registered Dual In-Line Memory Module (RDIMM)
2GB/4GB: 256Mx72/512Mx72 DDR3 Registered DIMM based on
256Mx8 DDR3 SDRAM B-Die devices
4GB/8GB: 512Mx72/1024Mx72 DDR3 Registered DIMM based
on 512Mx4 DDR3 SDRAM B-Die devices
16GB: 2Gx72 DDR3 Registered DIMM based on 1024Mx4 (DDP)
DDR3 SDRAM B-Die devices
Intended for 533MHz/667MHz applications
• Inputs and outputs are SSTL-15 compatible
VDD = VDDQ = 1.5V ± 0.075V (for DDR3)
VDD = VDDQ = 1.35V -0.0675/+0.1V (for DDR3L)
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
DRAM DLL aligns DQ and DQS transitions with clock transitions.
Address and control signals are fully synchronous to positive
clock edge
Nominal and Dynamic On-Die Termination support
• Programmable Operation:
- DIMM  Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
Two different termination values (Rtt_Nom & Rtt_WR)
15/10/1 (row/column/rank) Addressing for 2GB
15/11/1 (row/column/rank) Addressing for 4GB (512Mx4 Device)
15/10/2 (row/column/rank) Addressing for 4GB (256Mx8 Device)
15/11/2 (row/column/rank) Addressing for 8GB
15/11/4 (row/column/rank) Addressing for 16GB
Extended operating temperature rage
Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
SDRAMs are in 78-ball BGA Package
RoHS compliance and Halogen free
Description
NT2GC72B89B0NJ, NT2GC72B89B2NJ, NT2GC72C89B0NJ, NT2GC72C89B2NJ, NT4GC72B4PB0NL, NT4GC72C4PB0NL,
NT4GC72C4PB2NL, NT4GC72B8PB0NL ,NT4GC72C8PB0NL , NT4GC72C8PB2NL, NT8GC72B4NB1NJ,
NT8GC72B4NB3NJ ,NT8GC72C4NB1NJ, NT8GC72C4NB3NJ, NT16TC72B4NB1NL, NT16TC72C4NB1NL and NT16TC72C4NB3NL
are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Registered Dual In-Line Memory Module, organized as one rank of
256Mx72 (2GB), one rank or two ranks of 512Mx72 (4GB), two ranks of 1Gx72 (8GB) and four ranks of 2Gx72 (16GB) high-speed memory
array. Modules use nine 256Mx8 (2GB) 78-ball BGA packaged devices, eighteen 256Mx8 (4GB) 78-ball BGA packaged devices, thirty-six
512Mx4 (8GB) 78-ball BGA packaged devices and thirty-six 1Gx4 (DDP) (16GB) 78-ball BGA packaged devices. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25”
long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A14 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
12/2010
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.




Nanya Technology

NT4GC72B8PB0NL Datasheet Preview

NT4GC72B8PB0NL Datasheet

Registered DDR3 SDRAM DIMM

No Preview Available !

NT2GC72B89B0NJ/NT2GC72B89B2NJ/NT2GC72C89B0NJ/NT2GC72C89B2NJ
NT4GC72B4PB0NL/NT4GC72C4PB0NL/NT4GC72C4PB2NL/NT4GC72B8PB0NL/NT4GC72C8PB0NL/NT4GC72C8PB2NL
NT8GC72B4NB1NJ/NT8GC72B4NB3NJ/NT8GC72C4NB1NJ/NT8GC72C4NB3NJ
NT16TC72B4NB1NL/NT16TC72C4NB1NL/NT16TC72C4NB3NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 / 16GB: 2G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
Ordering Information
Part Number
NT2GC72B89B0NJ-CG
NT2GC72B89B2NJ-CG
NT4GC72B4PB0NL-CG
NT4GC72B8PB0NL-CG
NT8GC72B4NB1NJ-CG
NT8GC72B4NB3NJ-CG
NT16TC72B4NB1NL-BE
NT2GC72C89B0NJ-CG
NT2GC72C89B2NJ-CG
NT4GC72C4PB0NL-CG
NT4GC72C4PB2NL-CG
NT4GC72C8PB0NL-CG
NT4GC72C8PB2NL-CG
NT8GC72C4NB1NJ-CG
NT8GC72C4NB3NJ-CG
NT16TC72C4NB1NL-BE
NT16TC72C4NB3NL-BE
Speed
DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9)
DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9)
DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9)
DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9)
DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9)
DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9)
DDR3-1066 PC3-8500
533MHz (1.875ns @ CL = 7)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9)
DDR3L-1066 PC3L-8500 533MHz (1.875ns @ CL = 7)
DDR3L-1066 PC3L-8500 533MHz (1.875ns @ CL = 7)
Organization Power Leads Note
256Mx72
512Mx72
1Gx72
2Gx72
256Mx72
1.5V
Gold
512Mx72
1Gx72
2Gx72
1.35V
Pin Description
Pin Name
Description
Pin Name
Description
CK0, CK1
, 
Clock Inputs, positive line
Clock Inputs, negative line
ODT0, ODT1 Active termination control lines
DQ0-DQ63 Data input/output
CKE0, CKE1



-
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
DQS0-DQS17 Data strobes
- Data strobes complement
TDQS9-TDQS17 Termination data strobes
- Termination data strobes
DM0-DM8 Data Masks
A0-A9, A11, A13 Address Inputs
A10/AP Address Input/Auto-Precharge
A12/
Address Input/Burst Chop
CB0-CB7


ECC Check Bits
Temperature event pin
Reset pin
BA0-BA2
SCL
SDA
SDRAM Bank Address Inputs
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
VREFDQ , VREFCA Input/Output Reference
VDDSPD
SPD and Temp sensor power
SA0, SA1, SA2 Serial Presence Detect Address Inputs
Par_In
Parity bit for the Address and Control bus
Vtt Termination voltage
 Parity error found on the Address and Control bus VSS Ground
NC No Connect
VDD Core and I/O power
REV 1.2
12/2010
2
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.


Part Number NT4GC72B8PB0NL
Description Registered DDR3 SDRAM DIMM
Maker Nanya Technology
Total Page 30 Pages
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