NT5SV16M16BT Datasheet | Nanya Technology

.. NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Features - High Performance: 6K 75B Units CL=3 CL=3 f CK t CK t AC t AC Clock Frequency Clock Cycle Clock Access Time1 Clock Access Time2 166 6 - 5 133 MHz 7.5 - 5.4 ns ns ns 1. Terminated load. See AC Characteristics on page 37 2. Unterminated load. See AC Characteristics on page 37 3. t RP = t RCD = 2 CKs - Single Pulsed RAS Interface - Fully Synchronous to Positive Clock Edge - Four Banks controlled by BA0/BA1 (Bank Select) - - - - - - - - - - - - - - - - Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge mand Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 8192 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V ± 0.3V Power Supply LVTTL patible Package: 54-pin 400 mil TSOP-Type II Lead-free & Halogen-free product available Description The NT5SV64M4BS, NT5SV64M4BT, NT5SV32M8BS, NT5SV32M8BT, NT5SV16M16BS, and NT5SV16M16BT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are...